Superstrate sub-cell voltage-matched multijunction solar cells

ABSTRACT

Voltage-matched thin film multijunction solar cell and methods of producing cells having upper CdTe pn junction layers formed on a transparent substrate which in the completed device is operatively positioned in a superstate configuration. The solar cell also includes a lower pn junction formed independently of the CdTe pn junction and an insulating layer between CdTe and lower pn junctions. The voltage-matched thin film multijunction solar cells further include a parallel connection between the CdTe pn junction and lower pn junctions to form a two-terminal photonic device. Methods of fabricating devices from independently produced upper CdTe junction layers and lower junction layers are also disclosed.

CROSS REFERENCES

The present application is a continuation-in-part of InternationalApplication No. PCT/US12/68761 filed on Dec. 10, 2012, the contents ofwhich are incorporated by reference in their entirety.

CONTRACTUAL ORIGIN

The United States Government has rights in this invention under ContractNo. DE-AC36-08G028308 between the United States Department of Energy andAlliance for Sustainable Energy, LLC, the manager and operator of theNational Renewable Energy Laboratory.

BACKGROUND

In general, semiconductor-based photonic devices, such as photovoltaiccells (PV cells) include a junction formed between p-type and n-typeconductivity regions in a semiconductor body. These conductivity regionsgenerate a voltage potential and/or a current across the junction whenelectron-hole pairs are created in the semiconductor body in response tophotons impinging upon the photovoltaic cell. When a load is connectedbetween the p-type and n-type conductivity regions, an electric currentwill flow, thus producing power. PV cells therefore provide power from arenewable source, which is an attractive alternative to non-renewableenergy sources.

The power conversion efficiency of a PV cell consisting of a single pnjunction, referred to as a single junction solar cell, depends on thevoltage that can be generated by the pn junction and the ability of thesemiconductor(s) comprising the pn junction to absorb a significantportion of the solar spectrum. A semiconductor with a relatively largerbandgap energy can generate a large voltage, but photons having energiesless than the bandgap energy are not absorbed by the semiconductor, andthe generated current is relatively low. Likewise, a semiconductor witha relatively smaller bandgap energy can absorb a large portion of thesolar spectrum and generate a high current, but photon energy in excessof the bandgap energy is lost to thermal energy, and the output voltageof the single junction solar cell is low.

Combining multiple pn junctions within a PV cell to form what isreferred to as a multijunction solar cell can reduce the tradeoffsbetween voltage and current generation in a single junction solar celland increase the energy conversion efficiency of the device. In amultijunction solar cell, the pn junctions are typically arranged in avertically stacked configuration. The pn junctions may be stacked eitherthrough physical bonding or mechanical stacking of individual pnjunctions that have been grown on separate substrates, or throughmonolithic integration of the pn junctions on one substrate. Each pnjunction is designed to absorb a portion of the photons in the solarspectrum while passing photons with energy less than the bandgap energyto the pn junction(s) situated below. The use of multiple pn junctionsin a multijunction solar cell therefore reduces thermalization losses.Multijunction solar cells therefore typically have efficiencies that arehigher than single junction solar cells.

The manner in which the pn junctions that make up the multijunctionsolar cell are electrically connected together determines the voltageand current output of the device. A single pn junction solar cell can bepartitioned by subdividing it into multiple units of individual PV cellsarranged laterally, referred to as sub-cells. If the sub-cells areelectrically connected in series, their voltages add, and the lowestcurrent-producing sub-cell determines the overall current output of thedevice. If the sub-cells are electrically connected in parallel, thecurrents of each of the sub-cells add, and the voltage will be limitedto an intermediate voltage between the highest and lowest valuesproduced by any of the sub-cells. Multijunction solar cells may utilizeone or both of these electrical connection configurations.

Conventional multijunction solar cells are configured such thatvertically-stacked pn junctions are connected in series. These devicesare typically referred to as current-matched multijunction solar cellsbecause the individual pn junctions are usually designed to have thesame current output. In a monolithically integrated device, theelectrical connections between adjacent pn junctions are made with atunnel junction. The tunnel junction is an ultrathin pn junctioncomposed of heavily doped high bandgap energy p-type conductivity andn-type conductivity regions (heavily doped being defined herein asdopant concentrations of greater than about 10¹⁸ cm⁻³). From amanufacturing standpoint, tunnel junctions present a convenient way to“hard-wire” connections between vertically-stacked pn junctions, butachieving adequately high doping concentrations is difficult orimpossible in many semiconductor materials. This is particularly truefor many thin film semiconductors that are used in polycrystallinesingle junction and multijunction solar cells.

Voltage-matched multijunction solar cell designs can circumvent some ofthe limitations of current-matched designs. Variations in the solarspectrum throughout the day can have a large impact on the current thatis output by individual pn junctions, but spectral variations will havea much smaller impact on the voltage output. Therefore, the performanceof voltage-matched multijunction solar cells suffers less from diurnalspectral variations than current-matched multijunction solar cells.Moreover, tunnel junctions are not required between vertically-stackedpn junctions in a voltage matched design. This is advantageous whendesigning multijunction solar cells utilizing semiconductors in which itis difficult to achieve heavily doped ultrathin layers. The primarydisadvantage of voltage-matched multijunction solar cells, however, isthe need for more complex intra-cell electrical connections. Sub-cellsformed within the same pn-junctions are typically connected in series,forming a sub-cell string, and the strings from the different verticallystacked pn-junctions are then connected in parallel. The number ofsub-cells in each of the strings need not necessarily be the same andare chosen so that the voltage outputs of all of the strings match.Isolating and connecting sub-cells in pn junctions that are buriedwithin monolithically-integrated multijunction solar cell stacks ischallenging because it usually requires physical removal of materialfrom overlying pn junctions in order to access buried pn junctions. Inthese cases, fabrication requires multiple etch and growth steps, whichcan add to the cost of the solar cell module. It also necessarilyconstrains the geometry and layout of the sub-cells in each pn junctionlayer.

Polycrystalline or amorphous thin film solar cells, including cadmiumtelluride (CdTe), copper indium gallium selenide (sulfide) (CIGS),copper zinc tin sulfide (CZTS), polycrystalline or microcrystallinesilicon (Si) and amorphous Si (a-Si) architectures, have many advantagesover crystalline Si or III-V solar cell technologies. For example,polycrystalline or amorphous thin film designs feature relatively loweroverall material usage as compared to crystalline silicon cells, and theability to fabricate cells on large area glass substrates withatmospheric deposition techniques reduces manufacturing and modulecosts. One trade-off is that single junction polycrystalline and/oramorphous designs have comparatively lower conversion efficiencies thantheir crystalline Si or III-V counterparts.

Multijunction solar cell designs incorporating thin film materials wouldcapitalize on inexpensive processing costs while providing an avenue toincreased efficiencies over single junction polycrystalline or amorphousthin film solar cells. Thin film solar cell designs featuringmonolithically integrated structures in which the individual verticallystacked pn junctions are connected in series require that the output ofthese individual pn junctions be substantially current matched. As notedabove, this requirement necessitates that tunnel junctions are formedbetween the monolithically grown vertically stacked pn junctions tofacilitate current flow. However, difficulty in achieving heavily dopedultrathin layers in thin film materials impedes the formation of lowresistance tunnel junctions making the production of thin film currentmatched solar cells problematic. Furthermore, the complexity ofprocessing steps required by known prior-art voltage matched approaches(whether monolithic or mechanically stacked) makes known voltage matchedsolar cell technologies costly and thus unattractive.

The embodiments disclosed herein are intended to overcome one or more ofthe limitations described above. The foregoing examples of the relatedart and limitations related therewith are intended to be illustrativeand not exclusive. Other limitations of the related art will becomeapparent to those of skill in the art upon a reading of thespecification and a study of the drawings.

SUMMARY

The following embodiments and aspects thereof are described andillustrated in conjunction with systems, tools and methods which aremeant to be exemplary and illustrative, not limiting in scope. Invarious embodiments, one or more of the above-described problems havebeen reduced or eliminated, while other embodiments are directed toother improvements.

One embodiment includes a voltage-matched multijunction solar cellhaving a first (upper) crystalline, polycrystalline or amorphous pnjunction formed on a transparent substrate which is implemented in asuperstrate configuration, and an independently formed second (lower)crystalline, polycrystalline or amorphous pn junction. In thisembodiment, the first pn junction and the second pn junction of thesolar cell have a transparent electrically insulating layer locatedbetween the junction layers, and the first pn junction and second pnjunction are connected in parallel to form a two-terminal photonicdevice. In certain embodiments the upper pn junction comprises CdTejunction layers and the lower pn junction comprises crystalline Sijunction layers.

The voltage-matched solar cell may include front contacts and backcontacts associated with each pn junction accessible from the surface ofeach pn junction opposite the transparent electrically insulating layer.The contacts may be implemented with a transparent conducting oxide, ametal or by other means. The transparent superstrate may consist of butis not limited to a glass substrate, or a clear flexible substrate. Thecrystalline, polycrystalline or amorphous pn junctions may comprise atleast one of; CIGS, CZTS, a-Si, polycrystalline Si, microcrystalline Si,thin c-Si, CdTe, or CdTe alloyed with Zn, Se or S. The voltage-matchedthin film multijunction solar cell may also include a first string ofserially connected sub-cells defined within the first crystalline,polycrystalline or amorphous pn junction voltage matched to a secondstring of serially connected sub-cells defined within the secondcrystalline, polycrystalline or amorphous pn junction. The first stringis configured so that the substrate is positioned above the firstsub-cell string so that the first string connects to the second stringin a superstrate configuration.

One alternative embodiment comprises a voltage-matched thin filmmultijunction solar cell having a bottom pn junction formed from a dopedSi, Ge or GaAs wafer, interdigitated p-type and n-type back contactsassociated with the bottom pn junction and an insulating layer incontact with the bottom cell, opposite the back contacts. Thevoltage-matched thin film multijunction solar cell also includes anupper pn junction, a front contact and a back contact wherein the upperpn junction is separated from the bottom pn junction by an insulatinglayer and wherein the upper pn junction has a superstrate configurationwith a substrate above the upper pn junction, and the bottom pn junctionand the upper pn junction are connected in parallel to form atwo-terminal photonic device. In this embodiment, the front and backcontacts associated with the upper pn junction are accessible from thefront surface of the top cell and may comprise a transparent conductinglayer, for example, transparent conducting oxide layers or a metal gridlayer. In selected embodiments, the upper pn junction is a crystalline,polycrystalline or amorphous thin film CdTe upper junction. Thecrystalline, polycrystalline or amorphous upper pn junction may compriselayers of at least one of; CIGS, CZTS, a-Si, polycrystalline Si,microcrystalline Si, CdTe, or CdTe alloyed with Zn, Se or S. The bottompn junction may further comprise a thin crystalline Si pn junctionhaving a thickness of less than 80 micrometers.

Alternative embodiments include methods of fabricating the solar cellsdisclosed herein.

In addition to the exemplary aspects and embodiments described above,further aspects and embodiments will become apparent by reference to thedrawings and by study of the following descriptions.

BRIEF DESCRIPTION OF THE DETAILED DRAWINGS

Exemplary embodiments are illustrated in referenced figures of thedrawings. It is intended that the embodiments and figures disclosedherein are to be considered illustrative rather than limiting.

FIG. 1 is a simplified schematic illustration of a tandemvoltage-matched solar cell as disclosed herein;

FIG. 2 is a schematic illustration of the electrical connections betweenthe sub-cells illustrated in FIG. 1;

FIG. 3 is a schematic illustration of a tandem voltage-matched solarcell as disclosed here;

FIG. 4 is a schematic illustration of a tandem voltage-matched solarcell as disclosed herein;

FIG. 5 is a schematic illustration of a tandem voltage-matched solarcell having a CdTe p-n junction formed in a superstrate configuration;

FIG. 6 is a schematic illustration of a tandem voltage-matched solarcell having CdTe p-n junction formed in a superstrate configuration withc-Si sub-cells formed in an interdigitated back contact configuration;

FIG. 7 is a schematic illustration of a tandem voltage-matched solarcell having a CdTe p-n junction formed in a superstrate configurationwith c-Si bottom sub-cells formed from a thin c-Si layer;

FIG. 8 is a flow diagram of an exemplary method of manufacturing avoltage matched solar cell having a CdTe sub-cells in a superstrateconfiguration with bottom c-Si sub-cells.

FIG. 9 is a schematic illustration of a tandem voltage-matched solarcell having a CdTe p-n junction formed in a superstrate configurationwith a thin film bottom p-n junction.

DESCRIPTION

Unless otherwise indicated, all numbers expressing quantities ofingredients, dimensions, reaction conditions and so forth used in thespecification and claims are to be understood as being modified in allinstances by the term “about”.

In this application and the claims, the use of the singular includes theplural unless specifically stated otherwise. In addition, use of “or”means “and/or” unless stated otherwise. Moreover, the use of the term“including”, as well as other forms, such as “includes” and “included”,is not limiting. Also, terms such as “element” or “component” encompassboth elements and components comprising one unit and elements andcomponents that comprise more than one unit unless specifically statedotherwise. A material may be described herein as being “singlecrystalline”, “multicrystalline” or “polycrystalline”. Singlecrystalline very specifically means an ingot, wafer or epilayer that istruly a single crystal, with no grain boundaries. “Crystalline” is amore general term for a substantially crystalline material which canhave grain boundaries. “Multicrystalline” refers to a crystallinematerial with a small number of large crystalline grains.“Polycrystalline” refers to crystalline material comprised of a largenumber of small crystalline grains. The orientation of individual grainscan be arbitrary and the individual grains are separated by grainboundaries. The term single crystalline does not mean absolutely defectfree. Single crystalline material will have defects and/or dislocations.Certain abbreviations may be made herein with respect to the descriptionof semiconductor alloys. These abbreviations shall not be construed aslimiting the scope of the disclosure or claims. For example, the form“InGaAlN” is a common abbreviation to improve readability in technicalmanuscripts. Abbreviated forms such as “InGaAlN” are defined asequivalent to an expanded form, for example; “In_(x)Ga_(y)Al_(1-x-y)N”.

Multijunction (MJ) solar cells present the one option for significantlyincreasing absolute module efficiency beyond the single junctionSchockley Queisser limit of 32%. Combining different, low cost PVtechnologies (i.e. Si, CdTe, CIGS, etc) within an MJ solar cell couldprovide an alternative way to improve PV module efficiencies as well askeep manufacturing costs and complexity down. Specifically, combiningcrystalline, polycrystalline or amorphous Si and polycrystalline CdTe orother thin-film cells as described in detail below is advantageousbecause these are the most widely used PV technologies and thereforebenefit from the greatest knowledge and manufacturing bases. Si/thinfilm combination therefore present one of the best possibilities forachieving a levelized cost of electricity that is comparable toconventional energy sources, while being manufactured on a large scale.Incorporating these materials into a current-matched MJ solar cellconfiguration, however, is impractical because it is difficult to form ahigh performance tunnel junction between, for example tandem CdTe and Sisolar cells. The current-matching constraint also limits the design ofthe top and/or bottom sub-cells, potentially lowering the overallperformance of the device.

The embodiments disclosed herein provide a way to overcoming theselimitations by combining CdTe and Si pn junctions (or other materials asdescribed below) in a MJ solar cell by using a “voltage-matched”configuration. FIG. 1 shows the general architecture of avoltage-matched MJ (VMMJ) device 100. Arrays of sub-cells delineatedfrom the same absorber layer pn junction are serially connected intostrings and are separated from those of the other absorber layer pnjunction by an insulating barrier. The number of sub-cells in eachstring is engineered such that they output the same voltage (i.e.n₁V₁=n₂V₂), and the strings are connected in parallel to form a twoterminal device. The sub-cell dimensions can range from centimeters toseveral inches. The VMMJ design has the advantages that no tunneljunction is needed to connect the sub-cells, and the sub-cell geometrydoes not need to be adjusted to achieve current-matching requirements.Due to the diodes logarithmic I-V relationship, the output of VMMJ solarcells is also less sensitive to diurnal variations in the solar spectrumand intensity.

Known monolithically-integrated voltage-matched multijunction solarcells typically consist of a platform that includes many pn junctionsvertically stacked on top of a common substrate. Access to underlying pnjunctions for sub-cell isolation and contact formation therefore oftenoccurs in a top-down approach. According to some manufacturing anddeposition plans, isolation and metallization steps are designed tooccur after each pn junction is deposited or added. According to otherfabrication methods, all of the layers are first deposited or added, andtrenches are etched through one or more upper pn junctions in order toaccess underlying layers and pn junctions. These approaches necessarilyrequire a number of intricate processing steps that are costly. Theseapproaches also can introduce limitations in the geometricalconfiguration of the sub-cells in each pn junction and the way that thesub-cells are electrically connected.

As noted above, many multijunction solar cells are designed asmonolithically integrated structures in which the individual pnjunctions are connected in series and are current matched. This strategyrequires that heavily doped tunnel junctions be formed between the pnjunctions to facilitate current flow. However, difficulty in achievingheavily doped ultrathin layers in thin film materials impedes theformation of low resistance tunnel junctions if thin film pn junctionsare included in a current matched vertical stack. One way to overcomethis problem is to fabricate the multijunction solar cell in avoltage-matched configuration, for which parallel connections are madebetween the sub-cell strings that lie in different pn junctions. Notunnel junctions are needed, and the multijunction solar cells,typically fabricated with the individual pn junctions having selectedbandgaps as noted herein, exhibit a greater insensitivity to spectralvariations over the course of the day. In addition, the additivevoltages within a sub-cell string enables lower current densities at agiven power output. In concentrator applications, this feature is ofspecial value as it facilitates lower sheet current densities in thecontact layers and therefore lower I²R losses.

The various embodiments more specifically disclosed herein concern thedesign and fabrication of monolithically integrated multijunction solarcells in which strings of serially connected sub-cells havingapproximately equal output voltages are fabricated from two or morevertically stacked pn junctions which are connected in parallel. FIG. 1illustrates one possible embodiment 100 consistent with the principlesdisclosed herein. First and second pn junctions 102 and 104 respectivelyare separated by an electrically insulating transparent layer 106. Thepn junctions each consist of n-type and p-type conductivity regions andthe electrical junction between them. One region (p-type or n-type) isreferred to as the emitter, and the other region (n-type or p-type) isreferred to as the absorber. The materials for the pn junctions arechosen such that the bandgap energy of the semiconductor(s) comprisingthe first pn junction 102 is greater than the bandgap energy of thesemiconductor(s) comprising the second pn junction 104. The pn junction102 is operationally positioned to face the sun and is thereforealternatively referred to as the “upper,” “front” or “top” junctionherein. The bandgap energy of the material comprising the insulatinglayer 106 is also greater than that of the pn junction 104 and is equalto or greater than that of pn junction 102. Therefore, photons withenergies less than the bandgap energy of the pn junction 102 passthrough the pn junction 102 and insulating layer 106 to pn junction 104.In the device design of FIG. 1, one set of serially electricallyconnected sub-cell strings 108 is comprised of sub-cells fabricated frompn junction 102 and the other set of serially electrically connectedsub-cell strings 110 is comprised of sub-cells fabricated from pnjunction 104. Because the sub-cell voltage is a function of the bandgapenergy of the semiconductor(s) comprising the pn junction, the number ofserially connected sub-cells in each string is chosen such that the sumof sub-cell voltages in all of the strings in each pn junction isapproximately equal.

The serial electrical connections among sub-cells may be made in thefollowing manner. All electrical connections within the sub-cell strings108 in the top pn junction 102 are fabricated from the top side of thedevice. All electrical connections of the sub-cell strings 110 in thebottom pn junction 104 are fabricated from the backside of the device.The top sub-cell strings and bottom sub-cell strings are then connectedin parallel to form a two terminal device. The general configuration ofthe electrical connections of the sub-cells depicted in FIG. 1 isillustrated schematically in FIG. 2, where the diodes 202 and 204represent sub-cells in junctions 102 and 104 respectively. The precisesub-cell layout, electrical contact arrangement and fabricationprocesses will vary depending on the specific configuration andmaterials used in the monolithic tandem voltage-matched solar cell 100.The pn junctions may be fabricated from the substrate material, or grownon the substrate, or grown on a different substrate and subsequentlytransferred to the substrate used for the final monolithic tandemvoltage-matched solar cell 100. Substrates may include, but are notlimited to, a semiconductor wafer, glass or another opticallytransparent material. Processing steps may include, but are not limitedto, sub-cell isolation through chemical etching, laser scribing ormechanical scribing, material removal to expose and make electricalcontact to a buried contact layer and patterning electrically conductingand electrically insulating layers. The electrically conducting layersmay consist of a metal, a transparent conducting oxide or otherconducting material, among other choices. The insulating layers mayconsist of an un-doped semiconductor, oxide, nitride or other materialswith high electrical resistance. High resistivity or isolating diodescan also be used for electrical isolation of the two stacked pnjunctions. These insulating layers need to be transparent to light.

There are several benefits to the general monolithic tandemvoltage-matched solar cell design 100 presented in FIG. 1. One advantageis that the formation or interconnection of sub-cell strings within onepn junction layer can occur independently of the formation orinterconnection of sub-cell strings within the other pn junction layer.No material removal from the top pn junction 102 is needed to access theunderlying pn junction layer 104 for processing. Additionally, thegeometric configuration of sub-cells fabricated within the top pnjunction layer 102 is not dependent on the geometric configuration ofthe sub-cells fabricated within the bottom pn junction layer 104 or viceversa. Many single junction solar cells are also already fabricated suchthat all of the electrical contacts are made either from the front orfrom the back of the device. This is true of many thin film singlejunction solar cells grown on glass in a substrate or superstrateconfiguration as well as Si wafer-based single junction solar cellsfabricated with all back or interdigitated back contacts. The presentmonolithic tandem voltage-matched solar cell design approach allows forthe use of established processing routines with very little alteration.

Another embodiment of a voltage-matched monolithic solar cell is shownin FIG. 3. The FIG. 3 embodiment includes a monolithic tandemvoltage-matched solar cell 300 which can be fabricated from apolycrystalline or amorphous thin film pn junction, such as CIGS, CZTS,a-Si, polycrystalline Si, microcrystalline Si, CdTe, or CdTe alloyedwith Zn, Se or S, grown on or attached to a Si wafer-based pn junction.Strings of sub-cells 306 are formed in the lightly p-type (or n-type)doped Si wafer 304 using an all back or interdigitated back contactconfiguration, in which all contacts are made on the back side of the Siwafer 304. For example, heavily n-type doped regions (or heavily p-typedoped regions) 308 are patterned onto the backside of the Si wafer toform the emitter regions. Electrical connection to the lightly p-typedoped (or lightly n-type doped) Si absorber region may also befacilitated though the patterning of local regions 310 of heavy p-type(or n-type) doping on the backside of the Si wafer as well. Doping ofregions 308 and 310 may be achieved through a number of approachesincluding, but not limited to, dopant diffusion from Si inks, pastes orliquid dopant sources, ion implantation or amorphous Si deposition. Theheavily doped regions 308 and 310 are not restricted to any particularshape.

Metal contacts 312 and 314 are formed in contact with the doped regions308 and 310, respectively. Laser scribing, among other options, may beused to carry out sub-cell isolation. Texturing one or both sides of theSi wafer may be implemented to improve light absorption in the Sisub-cells. A heavily doped layer 316 with the same conductivity type asthe lightly doped Si wafer may also be included on the top side of theSi wafer in order to reduce carrier recombination at that interface.This may also be achieved by processes including, but not limited to,dopant diffusion from Si inks, pastes or liquid dopant sources, or ionimplantation, or amorphous Si deposition.

Electrical isolation of the bottom Si and the upper polycrystalline oramorphous sub-cell strings is achieved by forming an electricallyinsulating layer 318 on top of the Si wafer. This layer may be composedof an oxide or nitride material, an un-doped semiconductor or anotherelectrically insulating and optically transparent material. Theelectrical insulating layer 318 may also consist of a high resistivitylayer or isolating diode. Alternatively, low index of refraction layerscould also be utilized in the electrical insulating layer 318 to enhancephoton recycling and/or light trapping.

The upper polycrystalline or amorphous thin film pn junction is formedon top of the electrically insulating layer 318. The disclosedembodiments can be implemented with any of the existing polycrystallineor amorphous thin film single junction solar cell architectures, andfabrication of the sub-cell strings 302 from the pn junction 322 canfollow existing processing methods and routines. For example, thestructure may include a back contact layer 320, which may consist of,but not be limited to, a heavily doped semiconductor or a transparentconducting oxide that is transparent to photons with energies less thanthe bandgap energy of the polycrystalline or amorphous thin filmmaterial that comprises the pn junction of the top sub-cells. Thecontact layer 320 may be isolated into back contacts for individualsub-cells via laser scribing or chemical etching. The pn junction 322may be formed on top of the back contact layer 320. The pn junction ofeach sub-cell may then be isolated through laser scribing, chemicaletching or other means, such that an opening to the back contact layer320 is formed. An electrically conducting layer 324 may then bedeposited on top of the pn junction 322 to form the top contact as wellas the electrical connection to the back contact of the adjacentsub-cell when they are to be serially electrically connected to formsub-cell strings 302. The top contact layer 324 should be deposited orformed from a material that has a higher bandgap than the pn junction322 so that it is transparent to light absorbed in pn junction 322. Forexample, this material may include, but is not limited to, transparentconducting oxides. The top contact layer 324 may then be isolatedbetween sub-cells via laser scribing, chemical etching or other means.Metal grids may also be used in conjunction with or in place of the topcontact layer 324 to facilitate current collection from the topsub-cells. Metal contacts may also be used to connect adjacent sub-cellswithin a string. Finally, passive layers 326 may be deposited on top ofthe device to protect the top sub-cells. A similar layer could also beused on the back side of the device to passivate the bottom sub-cells ifneeded. Such layers could also incorporate a variety of photon recyclingor light trapping configurations. Post-deposition treatments may beapplied at any time during the processing to passivate defects in thepolycrystalline or amorphous material and improve the overallperformance of the sub-cells. The device structure may also includeadditional layers or features that are conventionally used to facilitatethe performance of silicon or thin-film solar cells but are not shown inFIG. 3.

The use of a Si wafer to fabricate the bottom sub-cells has manyadvantages including but not limited to the following:

-   -   An interdigitated back contact (IBC) or other strategy which        positions both the n-type contacts 312 and the p-type contacts        314 on the back side of the device (or away from the insulating        layer 318) can be used to facilitate contacting and improve        light absorption in the Si active layers. Implementation of an        IBC can be carried out at low cost using Si ink technologies,        which allow screen-printing of patterned n-type and p-type        contacts in close proximity to one another. Dopant diffusion        from pastes or liquid dopant sources, ion implantation or        amorphous Si deposition could also be used to create regions of        high doping for the IBC. In the IBC embodiment, isolation of the        Si sub-cells can also occur from the back-side of the device,        which will reduce the complexity of the isolation processing        steps. A heavily doped layer 316 can also be incorporated into        the Si sub-cells at the interface with the isolation layer 318        to reduce carrier recombination. Alternatively, transparent        conducting layers and/or selective emitter technologies could be        used to form the front contact of the Si active layers.    -   Planar or textured geometries can be used for the Si layers. The        later improves the absorption of long wavelength light via        light-trapping effects. A textured surface should also not        significantly affect the subsequent deposition of the upper        polycrystalline or amorphous pn junction layer.

The bandgap energies of the materials comprising the pn junctions in themonolithic tandem voltage-matched solar cells of FIG. 3 can span therange of 0.25 eV to 2.5 eV. However, the ideal combination of bandgapenergies for a tandem solar cell under one sun illumination isapproximately 1.1 eV and 1.7 eV. The bandgap energy of Si is near theideal 1.1 eV value for a bottom sub-cell. A wafer of Ge or any othercrystalline semiconductor may also be used in the place of a Si waferfor the bottom sub-cells, but this may increase the cost of the device.A number of polycrystalline or amorphous thin film materials may be usedfor the top sub-cells. CdTe (1.45 eV) has a bandgap energy that isslightly lower than the ideal value but would still be viable. CdTe mayalso be alloyed with Zn, Se or S to increase the bandgap energy. Otherpossible thin film materials may include, but are not limited to,polycrystalline CIGS (0.9-2.5 eV), CZTS (1.4-15. eV), a-Si (1.7 eV), ormicrocrystalline Si. These materials have the advantage that they do notneed to be grown on a crystalline template, and no lattice-matching isrequired.

Thin single crystalline or large-grained multicrystalline semiconductorlayers may also be utilized as the pn junction material for the topsub-cell strings in the embodiments shown in FIG. 3. Thin singlecrystalline or large-grained multicrystalline semiconductor layers mayinclude, but are not limited to, GaAs_(x)P_(1-x), GaIn_(x)P_(1-x), GaAs,CdTe, CdSe, ZnTe, CIGS or CZTS. These crystalline pn junctions may bemetamorphically grown directly on a crystalline electrically insulatinglayer 318 with the potential use of a compositionally-gradedtransitional buffer (CGTB) layer. A CGTB layer is designed toaccommodate large differences in lattice constants between twocrystalline materials that may cause defects by gradually shifting thelattice constant between the values of the electrically insulatingmaterial 318 and pn junction 322. The CGTB layer is designed to betransparent to light passing through the top pn junction 322 to thebottom pn junction. In this embodiment, the back contact layer 320associated with the top pn junction 322 may also consist of a heavilydoped single crystalline semiconductor. The CGTB layer may also be usedbetween the top of the heavily doped layer in the bottom sub-cell wafer316 and the electrically insulating layer 318, the electricallyinsulating layer 318 and the back contact layer 320, the back contactlayer 320 and the pn junction 322 of the top sub-cells or anycombination thereof. The single crystalline or large-grainedmulticrystalline pn junction 322 may also be grown on a differentsubstrate designed to template crystalline growth and subsequentlytransferred and bonded to the final device structure. This allows forflexibility in choosing the materials of the electrically insulatinglayer 318 and back contact layer 320. Neither layer is required to besingle crystalline or large-grained multicrystalline in this case. Ifthese layers are implemented with single crystalline materials, however,they may be grown on the final device structure itself or on the samesubstrate that is used for the growth of the crystalline pn junction322. A single crystalline or large-grained multicrystalline electricallyinsulating layer 318 or back contact layer 320 may also be grown on adifferent substrate entirely, in which case it also would have to betransferred and bonded to the final device structure. In addition, thepn junction 322 may consist of several pn junction layers connected inseries via tunnel junctions instead of a single pn junction layer. Theset of vertically stacked pn junctions that make up 322 would constitutea single sub-cell that would be serially connected to neighboringsub-cells in 322 in the same manner as outlined above for the case wherethe pn junction 322 consists of a single pn junction.

In another embodiment, a monolithic tandem voltage-matched solar cellcan be fabricated from two polycrystalline and/or amorphous thin film pnjunctions separated by an electrically insulating substrate. A schematicrepresentation of an example device design 400 is shown in FIG. 4. Thebottom sub-cell strings 402 are configured in a superstrate designapproach on a transparent substrate 404, while the top sub-cell strings406 are configured in a substrate design approach on top of thetransparent substrate 404. The bottom sub-cell string 402 has anassociated transparent front contact layer 408 deposited on the backsideof the transparent substrate 404. The bottom pn junction 410 isdeposited on the front contact layer 408 and the bottom contact layer412 is deposited on the bottom pn junction 410. Patterning, etching, orscribing of these layers may occur in any sequence during thefabrication of the bottom sub-cells. The bottom sub-cells are connectedin series to form sub-cell strings with the desired number of sub-cellsto achieve a required voltage. The top sub-cell strings 406 are formedfrom a transparent back contact layer 414, a pn junction 416 and atransparent front contact layer 418. Patterning, etching, or scribing ofthese layers may occur in any sequence during the fabrication of the topsub-cells. The top sub-cells are connected in series to form sub-cellstrings with the desired number of sub-cells to achieve a requiredvoltage.

The polycrystalline or amorphous materials grown or deposited to formthe top and bottom pn junctions 416 and 410, respectively, may consistof, but are not limited to, CIGS, CZTS, CIS, a-Si, polycrystalline Si,microcrystalline Si, CdTe, or CdTe alloyed with Zn, Se or S. Both thetransparent back contact layer 414 of the top sub-cells and the frontcontact layer 408 of the bottom sub-cells should be transparent tophotons with energy less than those absorbed by the top pn junction 416.These layers may be fabricated from materials including but not limitedto transparent conducting oxides. The transparent substrate 404 may beglass or any other material that is transparent to photons with energyless than those absorbed by the top pn junction 416. The transparentsubstrate 404 may act as the electrically insulating layer, or aseparate electrically insulating layer may be deposited anywhere betweenthe front contact 408 of the bottom pn junction and the back contact 414of the top pn junction. As noted above, layers or configurations thatsupport photon recycling and/or light trapping could also beincorporated into top and bottom sub-cells.

One advantage provided by a monolithic tandem voltage-matched solar cell400 is that the polycrystalline or amorphous pn junction can be grown ordeposited directly on an inexpensive and readily available substratesuch as glass. This design provides the efficiency boost of integratingtwo polycrystalline or amorphous thin film single junction solar cellsinto a multijunction solar cell while maintaining a one sun, flat plateconfiguration with a relatively low module cost. Single crystalline orlarge-grained multicrystalline layers can also be used for the top pnjunction 416, bottom pn junction 410 or both in this design by usinglayer transfer techniques. The crystalline pn junction can be grown on asingle or multicrystalline template substrate. These layers can then bedetached from the template substrate and bonded to the final devicestructure. This approach offers a greater selection of semiconductormaterials in order to tune the bandgap energy or performance of the topand/or bottom sub-cells. The front and back contacts to each of the pnjunctions may be made in any manner that is necessary for fabricatingsub-cells out of crystalline pn junctions. This includes the sub-celldesign, processing steps and material used for the top and bottomcontacts. Metal grids may be used in place of or in addition to the lowelectrical resistivity front or back contact layers as required. Allback contact or interdigitated back contact designs can also be used forthe bottom sub-cells in this embodiment. Pn junction layers 416 and 410could also comprise vertically stacked sets of pn junctions that areconnected in series via tunnel junctions.

The various solar cell embodiments disclosed herein includevoltage-matched multijunction solar cell designs and devices containingat least one polycrystalline or amorphous thin film pn junction layer.This enables several device design enhancements, including but notlimited to:

-   -   The ability to grow polycrystalline or amorphous thin films on        non-crystalline surfaces allows for the use of non-crystalline        transparent conducting contacts to be incorporated into the        device stack.    -   Elimination of the need for a crystalline growth template for        the polycrystalline or amorphous thin film layers also allows        for the incorporation of many different PV technologies and        their associated efficiency-enhancing design improvements. This        includes the use of inexpensive, non-crystalline substrates,        such as glass, and light trapping features for embodiments that        incorporate a crystalline Si pn junction. Eliminating the        dependence on a crystalline growth template also obviates the        need for thick CGTB layers and reduces the growth complexity and        material usage in the device.    -   In addition, the connection of pn junctions in parallel instead        of series eliminates the need for heavily doped tunnel        junctions, which is a major impediment to the development of        thin film multijunction solar cells.

Certain VMMJ solar cell designs disclosed below incorporate a CdTe toppn junction and a bottom pn junction composed of bulk c-Si, thin filmc-Si or another thin film material. In each case, the CdTe pn junctionis assumed to be fabricated from a polycrystalline CdTe (absorber) andpolycrystalline cadmium sulfide (CdS) (emitter/window layer). However,these layers could also be single crystalline. The Si pn junction isassumed to be crystalline (c-Si). This could be single crystalline,multicrystalline or polycrystalline in a wafer, thin layer,layer-transferred or other form. The Si emitter may be formed by anymethod, including high temperature dopant diffusion, c-Si epitaxy, ordeposition of intrinsic and heavily doped amorphous Si layers (HIT celldesign). Any suitable method or combination of methods for growing,depositing and/or fabricating the pn junction layers may be used.Likewise, the thin film bottom sub-cells can, in alternativeembodiments, include a pn junction formed from polycrystalline thin filmmaterial(s) (i.e. CIGS, CZTS or another material) on a suitablesubstrate by any suitable fabrication method. The contacts can be formedfrom metal grids, transparent conducting materials or other contactingmethods. The back contact of the bottom sub-cells may also be formedfrom a metal layer. The top contact of the CdTe sub-cells will typicallybe transparent to photons with energies above the CdTe bandgap, whereasthe bottom contact of the CdTe sub-cells should primarily be transparentto photons with energies below the CdTe bandgap in order for this thesephotons to reach the underlying c-Si sub-cells. Contacts therefore canbe formed from transparent conducting materials and/or metal grids thatare designed to minimize optical shading. Likewise, the top contacts forthe c-Si or thin film sub-cells (if used) should also be transparentand/or be designed to minimize optical shading losses. Any process ofdepositing or otherwise forming the contacts may be used. Thetransparent, electrically insulating barrier described in detail below,positioned between the top and bottom pn junctions, can be formed fromany material and process that is suitable for that purpose. Theinsulating layer or layers between sub-cells may also be formed from acombination of materials that, in addition to being transparent andelectrically insulating, also promote light trapping or lighttransmission.

Sub-cell stacking or integration may be carried out in two generalapproaches. Multiple sub-cells may be defined and interconnected withina single continuous pn junction layer, as depicted in FIG. 1. Sub-cellisolation may be performed by any suitable method, including dry or wetetching, laser scribing, mechanical scribing or other methods.

One particular embodiment of a voltage-matched multijunction solar cellhaving CdTe upper pn junction layers and c-Si lower junction layers isshown in FIG. 5. The FIG. 5 embodiment includes upper junction layersprepared in a superstrate configuration. More particularly, the FIG. 5embodiment is a tandem voltage-matched multijunction solar cell 500fabricated from upper sub-cells defined within a set of polycrystallinethin film CdTe pn junction layers 502, such as CdTe, or CdTe alloyedwith Zn, Se or S, grown on a transparent substrate 512. The Si pnjunction layers 504 are formed independently from the CdTe pn junctions504. When the device is assembled, CdTe and Si pn junctions 502 and 504respectively are separated by an electrically insulating transparentlayer 506. The voltage-matched multijunction solar cell 500 isstructurally similar to solar cell 100 of FIG. 1, one difference beingthat the CdTe (upper) pn junction 502 is formed independently from theSi (lower) pn junction 504 with the respective sub-cells being joinedinto a device 500 in a subsequent step. Therefore, the CdTe pn junction502 may be implemented for use in a superstrate configuration, and theSi pn junction 504 formed and implemented in a substrate configuration.

Specifically, the CdTe pn junction 502 may be formed on a separatetransparent substrate 512, glass for example, subsequently inverted andbonded to the insulating layer above the top of Si pn junction 504.Therefore, the growth substrate 512 is positioned as an operationalsuperstrate which in use faces the sun.

In the specifically illustrated configuration of solar cell 500, one setof serially electrically connected sub-cell strings 508 is comprised ofCdTe sub-cells fabricated from CdTe pn junction 502 and the other set ofserially electrically connected sub-cell strings 510 is comprised of Sisub-cells fabricated from Si pn junction 504. Because the sub-cellvoltage is a function of the bandgap energy of the semiconductor(s)comprising the pn junctions 502 and 504, the number of seriallyconnected sub-cells in each string is chosen such that the sum ofsub-cell voltages in all of the strings in each pn junction isapproximately equal.

The serial electrical connections among sub-cells may be made in thefollowing representative, but non-limiting manner. All electricalconnections within the sub-cell strings 508 in the CdTe pn junction 502are fabricated on transparent substrate 512. All electrical connectionsof the sub-cell strings 510 in the Si pn junction 504 are fabricated ona separate substrate. Each of the CdTe sub-cells of sub-cell string 508is serially connected, and each of the Si sub-cells of sub-cell string510 is serially connected. The top sub-cell strings 508 and bottomsub-cell strings 510 are then connected in parallel to form a twoterminal device.

The precise sub-cell layout, electrical contact arrangement andfabrication processes utilized will vary depending on the specificconfiguration and materials used in the tandem voltage-matchedmultijunction solar cell 500. As noted above, the CdTe pn junction 502may be fabricated on transparent substrate 512. Si pn junction 504 isindependently fabricated from a separate substrate, or grown on aseparate substrate and subsequently transferred to the tandemvoltage-matched multijunction solar cell 500. In some embodiments, theSi pn junction 504 may be prepared separately, transferred andsubsequently bonded to the transparent electrically insulating layer506. Alternatively, the transparent electrically insulating layer 506may be grown on one of the Si pn junction 504 or CdTe sub-cell string508 and then bonded to the other sub-cell as a fabrication step.

Substrates useful for either the upper or lower sub-cells may include,but are not limited to, a semiconductor wafer, glass, a polymer oranother material which is optically transparent and which may be rigidor flexible. Processing steps may include, but are not limited to,sub-cell isolation through chemical etching, laser scribing ormechanical scribing, material removal to expose and make electricalcontact to a buried contact layer and patterning electrically conductingand electrically insulating layers. The electrically conducting layersmay consist of a metal, a transparent conducting oxide or otherconducting material, among other choices. The insulating layers, such astransparent electrically insulating layer 506, may consist of anun-doped semiconductor, oxide, nitride, polymer or other material withhigh electrical resistance and optical transparency at suitablewavelengths. High resistivity or isolating diodes can also be used forelectrical isolation of the two stacked pn junctions.

There are several benefits to the use a CdTe pn junction in asuperstrate configuration, as shown in FIG. 5. One advantage notedabove, is that the CdTe pn junction can be formed independently from theSi pn junction. This prevents the sub-cells of one PV technology frombeing exposed to the processing and fabrication conditions of the other.Additionally, the pn junctions may be formed in parallel with eachother, thus simplifying the manufacturing process of having to createthe pn junctions 502 and 504 on either side of the same substrate.Standard fabrication processes used commonly by industry formanufacturing single junction CdTe and Si solar cells can be used inpart to fabricate the pn junctions 502 and 504 separately.

The superstrate CdTe sub-cells strings 508 of FIG. 5 may be formeddirectly from CdTe pn junction 502. For example, the structure mayinclude a front contact layer 522 that should be deposited or formedfrom a material with a higher bandgap than the CdTe pn junction 502 sothat it is transparent to light absorbed in CdTe pn junction 502. Forexample, this material may include, but is not limited to, transparentconducting oxides. The front contact layer 522 is formed on transparentsubstrate 512, and may be isolated into front contacts for individualsub-cells via laser scribing or chemical etching. The CdTe pn junction502 may be formed on top of the front contact layer 522. The pn junctionof each sub-cell may then be isolated through laser scribing, chemicaletching or other means, such that an opening to the front contact layer522 is formed.

An electrically conducting back contact layer 520 may then be depositedon top of the CdTe pn junction 502 to form the back contact as well asthe electrical connection to the front contact of the adjacent sub-cellwhen they are to be serially electrically connected to form sub-cellstrings 508. The back contact layer 520 may consist of, but is notlimited to, a heavily doped semiconductor or a transparent conductingoxide that is transparent to photons with energies less than the bandgapenergy of the polycrystalline or amorphous thin film material thatcomprises the CdTe pn junction 502 of the superstrate CdTe sub-cellstring 508. For example, this material may include, but is not limitedto, transparent conducting oxides. The back contact layer 520 may thenbe isolated between sub-cells via laser scribing, chemical etching orother means. Metal grids may also be used in conjunction with or inplace of the transparent back contact layer 520 to facilitate currentcollection from the top sub-cells. Metal contacts may also be used toconnect adjacent sub-cells within a string. In a superstrateconfiguration, transparent substrate 512 protects the top sub-cells.Transparent substrate 512 could optionally incorporate a variety ofphoton recycling or light trapping configurations. Post-depositiontreatments may also be applied at any time during the processing topassivate defects in the polycrystalline material and improve theoverall performance of the CdTe sub-cells.

The Si lower sub-cells can be formed similarly, having front contact 524and bottom contact 526. Once formed, the Si lower sub-cells aresubsequently transferred and bonded to the CdTe upper sub-cell string,as described in further detail below with respect to FIGS. 6 and 8.

FIG. 6 illustrates a voltage-matched multijunction solar cell 600 havinga CdTe sub-cell string 602 in a superstrate configuration, and bottom Sisub-cell string 606 formed in an interdigitated back contact (IBC)configuration. The solar cell 600 contains similar structures to solarcell 300 of FIG. 3 with the exception of the CdTe sub-cell string 602being configured in a superstrate configuration, with transparentsubstrate 626 operationally positioned above the CdTe sub-cells.

Si sub-cell string 606 is formed independently of CdTe sub-cell string602 from Si wafer 604. Si sub-cells are fabricated to have an IBCconfiguration. For example, sub-cell string 606 is formed in the lightlyp-type (or n-type) doped Si wafer 604 using an all back or IBCconfiguration, in which all contacts are made on the back side of the Siwafer 604. For example, heavily n-type doped regions (or heavily p-typedoped regions) 608 are patterned onto the backside of the Si wafer toform the emitter regions. Electrical connection to the lightly p-typedoped (or lightly n-type doped) Si absorber region may also befacilitated though the patterning of local regions 610 of heavy p-type(or n-type) doping on the backside of the Si wafer as well.

Metal contacts 612 and 614 are formed in contact with the doped regions608 and 610, respectively. Laser scribing, among other options, may beused to carry out sub-cell isolation. Texturing one or both sides of theSi wafer may be implemented to improve light absorption in the Sisub-cells. A heavily doped layer 616 with the same conductivity type asthe lightly doped Si wafer may also be included on the top side of theSi wafer in order to reduce carrier recombination at that interface.This may also be achieved by processes including, but not limited to,dopant diffusion from Si inks, pastes or liquid dopant sources, ionimplantation, or amorphous Si deposition.

Si sub-cell string 606 can subsequently be transferred and bonded toCdTe sub-cell string 602. In some embodiments, the Si sub-cell string606 may be transferred and subsequently bonded to the transparentelectrically insulating layer 618, or transparent electricallyinsulating layer 618 may be grown on the Si wafer 604 and bonded to CdTesub-cell string 602. In some embodiments, transparent electricallyinsulating layer 618 may be an oxide grown on the Si wafer 604, which isthen bonded to CdTe sub-cell string 602. In other embodiments, thetransparent electrically insulating layer 618 may be a piece of plasticplaced between the sub-cell strings 602 and 606. Any suitable means ofphysically connecting the two sub-cell strings 602 and 606 may be used.In one embodiment, CdTe sub-cell string 602 is bonded to Si sub-cellstring 606 using polyethylene terephthalate.

CdTe sub-cell string 602 can be formed separately on transparentsubstrate 626 for implementation in a superstrate configuration, asdescribed above with respect to FIG. 5, and as described below withrespect to FIG. 8.

FIG. 7 illustrates an alternative voltage-matched multijunction solarcell 700 having a CdTe sub-cell string 708 positioned in a superstrateconfiguration, and a thin c-Si sub-cell string 710 formed from a thinc-Si layer 704, typically but not exclusively less than 80 micrometers(μm) in thickness. These layer(s) 704 may be formed by any appropriatemethod. For example, in some embodiments, the layer(s) 704 are formed bysawing appropriately thin wafers from a Si boule. In yet otherembodiments, c-Si layer(s) 704 may be formed by removing a thin layerdirectly from a Si boule by a kerfless method, depositing thecrystalline layer(s) 704 from the gas or solid phase on a c-Si templateand then removing the layer(s) 704 from the template through the use ofan engineered “release layer.” Alternatively, the crystalline layer(s)704 may be deposited from a gas or solid phase precursor on a foreigncrystalline template. The geometry of the thin c-Si sub-cells may beeither in the conventional arrangement (front emitter, front and backcontacts) or an IBC configuration.

The use of thin c-Si sub-cells has the advantage that less material isconsumed, which has the potential to lower the cost of the module.Moreover, physical supporting for the thin c-Si sub-cell string 710 isprovided by the CdTe superstrate sub-cell string 708. However,additional light trapping designs may also need to be incorporated tomaximize light absorption in these thin c-Si sub-cells.

The CdTe sub-cells of device 700 are formed on a separate substrate 712.All electrical connections within the sub-cell string 708 in the CdTe pnjunction layers 702 are fabricated on transparent substrate 712 beforebeing combined with thin c-Si sub-cell string 710.

The CdTe sub-cells 702 and the c-Si sub-cells 704 are fabricatedindependently and/or in parallel before integration, thus preventing thesub-cells of one PV technology from being exposed to the processingconditions of the other.

Si sub-cell string 710 can subsequently be transferred and bonded toCdTe sub-cell string 708. In some embodiments, the Si sub-cell string710 may be transferred and subsequently bonded to the transparentelectrically insulating layer 706, or transparent electricallyinsulating layer 706 may be grown on the c-Si layer(s) 704 and bonded toCdTe sub-cell string 708. The transfer, bonding and other fabricationsteps utilized to create the device 700 or other devices disclosedherein may be performed in any suitable order. In certain embodiments,some processing steps described herein may be eliminated or additionalprocessing steps may be performed. In addition, in some embodimentsadditional processing or finishing steps may be performed after theupper and lower sub-cell strings have been transferred and bonded. Insome embodiments, transparent electrically insulating layer 706 may bean oxide grown on the c-Si layer(s) 704. In other embodiments, thetransparent electrically insulating layer 706 may be a piece of plasticplaced between the sub-cell strings 708 and 710. In one embodiment, CdTesub-cell string 708 is bonded to Si sub-cell string 710 usingpolyethylene terephthalate. The polyethylene terephthalate layer mayalso be used to physically support the Si layer(s) during the transferprocess. Any suitable means of physically connecting the two sub-cellstrings 708 and 710 may be used.

An exemplary method 800 of fabricating certain of the above embodimentsis illustrated in FIG. 8. At block 801, a transparent substrate isprovided. The transparent substrate may include, but are not limited to,a semiconductor wafer, glass, a polymer or another material which isoptically transparent and which may be rigid or flexible. Whenoperatively implemented in a superstrate configuration, the transparentsubstrate protects the top CdTe sub-cells. The transparent substratecould optionally incorporate a variety of photon recycling or lighttrapping configurations.

At block 803, CdTe upper sub-cells are formed on the transparentsubstrate. In one embodiment, the CdTe upper sub-cell may comprise aCdTe absorber layer and a CdS emitter layer. In various embodiments, informing CdTe sub-cells, an electrically conducting front contact layeris deposited onto the substrate. The front contact should be depositedor formed from a material that has a higher bandgap than the CdTe pnjunction so that it is transparent to light absorbed in CdTe pnjunction. For example, this material may include, but is not limited to,transparent conducting oxides. The front contact layer may be isolatedinto front contacts for individual sub-cells via laser scribing orchemical etching. A CdTe pn junction is formed on top of the frontcontact layer. The pn junction of each sub-cell may then be isolatedthrough laser scribing, chemical etching or other means, such that anopening to the front contact layer.

A back contact layer may be deposited on top of the CdTe pn junction toform the back contact as well as the electrical connection to the frontcontact of the adjacent sub-cell when they are to be seriallyelectrically connected to form sub-cell strings. The back contact layermay include, but is not limited to, a heavily doped semiconductor or atransparent conducting oxide that is transparent to photons withenergies less than the bandgap energy of the polycrystalline oramorphous thin film material that comprises the CdTe pn junction. Theback contact layer may then be isolated between sub-cells via laserscribing, chemical etching or other means. Metal grids may also be usedin conjunction with or in place of the back contact layer to facilitatecurrent collection from the top sub-cells. Metal contacts may also beused to connect adjacent sub-cells within a string. Post-depositiontreatments may also be applied at any time during the processing topassivate defects in the polycrystalline material and improve theoverall performance of the CdTe sub-cells.

At block 805, lower Si sub-cells are formed independently of the CdTeupper sub-cells. That is, the Si sub-cells are formed in a separateprocess from the CdTe upper sub-cells and may be fabricatedsimultaneously and in parallel with the CdTe fabrication process.

In one embodiment, the Si lower sub-cells can be formed on a separatesubstrate. The lower Si sub-cells may be formed to have a front contactand bottom contact. In certain embodiments, the Si sub-cell string isformed from a Si wafer.

In various other embodiments, the Si sub-cell may be fabricated in anIBC configuration. For example, all electrical contacts may be made onthe back side of the Si wafer. Heavily n-type doped regions (or heavilyp-type doped regions) are patterned onto the backside of the Si wafer toform the emitter regions. Electrical connection to the lightly p-typedoped (or lightly n-type doped) Si absorber region may also befacilitated though the patterning of local regions of heavy p-type (orn-type) doping on the backside of the Si wafer as well. Metal contactsmay then be formed in contact with the heavily doped regions,respectively. Laser scribing, among other options, may be used to carryout sub-cell isolation.

In some further embodiments, a thin c-Si lower sub-cell may be formedfrom a thin c-Si layer, which is typically, but not exclusively, lessthan 80 micrometers (μm) in thickness. These layer(s) may be formed byany appropriate method, including, but not limited to, by sawingappropriately thin wafers from a Si boule, removing a thin layerdirectly from a Si boule by a kerfless method, depositing thecrystalline layer(s) from the gas or solid phase on a c-Si template andthen removing the layer from the template through the use of anengineered “release layer,” or depositing from a gas or solid phaseprecursor on a foreign crystalline template. The geometry of the thinc-Si sub-cells may be either in the conventional arrangement (frontemitter, front and back contacts) or an IBC configuration. In thisembodiment, the Si lower sub-cells may be physically supported and/orreinforced by the CdTe upper sub-cells.

Texturing one or both sides of the Si wafer may be implemented toimprove light absorption in the Si sub-cells. A heavily doped layer withthe same conductivity type as the lightly doped Si wafer may also beincluded on the top side of the Si wafer in order to reduce carrierrecombination at that interface. This may also be achieved by processesincluding, but not limited to, dopant diffusion from Si inks, pastes orliquid dopant sources, ion implantation, or amorphous Si deposition.

At block 807, a transparent insulating layer is provided between CdTe pnjunction layers and the Si pn junction layers. In some embodiments, theinsulating layer may consist of an un-doped semiconductor, oxide,nitride, polymer or other material with high electrical resistance andoptical transparency at suitable wavelengths. High resistivity orisolating diodes can also be used for electrical isolation of the twostacked pn junctions.

In some embodiments, the Si sub-cells can be transferred andsubsequently bonded to the transparent electrically a separateinsulating layer, such as a piece of plastic such as polyethyleneterephthalate. In other embodiments, the transparent electricallyinsulating layer may be grown on the Si wafer, for example as an oxidelayer.

At block 809, the CdTe pn junction layers are joined to the Si pnjunction layers, with the CdTe pn junction layers/sub-cells positionedin a superstrate configuration. Any suitable means of physicallyconnecting the two pn junction layers/sub-cell strings may be used. Insome embodiments, Si sub-cells can be transferred after fabrication, andsubsequently bonded to the transparent insulating layer. In otherembodiments, the transparent insulating layer may be grown on the Sisub-cells and the CdTe sub-cells subsequently bonded to the oxidetransparent insulating layer in a superstrate configuration.

At block 811, the CdTe upper sub-cell strings and Si lower sub-cellstrings are electrically connected in parallel to create a two terminalvoltage-matched device. Thus, the total voltage of each CdTe uppersub-cell strings is equal to the total voltage of each Si lower sub-cellstrings. It is important to note that in certain fabrication methodembodiments, some processing steps described herein may be eliminated oradditional processing steps may be performed. In addition, in somefabrication method embodiments, additional processing or finishing stepsmay be performed after the upper and lower sub-cell strings have beentransferred and bonded.

In an alternative embodiment of voltage-matched multijunction solar cell900 illustrated in FIG. 9, the bottom sub-cells 902 may be formed frompn junctions 904 fabricated with thin film materials such as CIGS, CZTS,CIS or other suitable semiconductors. These bottom sub-cells 902 can befabricated on any suitable substrate 906 using any deposition andsub-cell isolation methods. Any suitable method may also be used toserially connect the thin film bottom sub-cells 902 into strings. Thebottom thin film sub-cells 902 can then be connected to the top CdTesub-cells 908, fabricated as described above, via an intermediate,electrically insulating layer 910. Thus, the superstrate 912 of the topCdTe sub-cells 908 may support the bottom sub-cells 902 forpost-stacking processing or finishing steps. Electrically insulatinglayer 910 could be a polyethylene terephthalate layer or some otherplastic, or it could be an oxide deposited on one of the surfacesbetween the bottom and top sub-cells.

The description of the disclosed embodiments has been presented forpurposes of illustration and description, but is not intended to beexhaustive or limiting of the claims to any particular form disclosed.The scope of the present disclosure is limited only by the scope of thefollowing claims. Many modifications and variations will be apparent tothose of ordinary skill in the art. The embodiments described and shownin the figures were chosen and described in order to best explain theprinciples of the various embodiments, the practical application, and toenable others of ordinary skill in the art to understand the variousembodiments with various modifications as are suited to the particularuse contemplated.

While a number of exemplary aspects and embodiments have been discussedabove, those of skill in the art will recognize certain modifications,permutations, additions and sub combinations thereof. It is thereforeintended that the following appended claims and claims hereafterintroduced are interpreted to include all such modifications,permutations, additions and sub-combinations as are within their truespirit and scope of the disclosure. Various embodiments of thedisclosure could also include permutations of the various elementsrecited in the claims as if each dependent claim was a multipledependent claim incorporating the limitations of each of the precedingdependent claims as well as the independent claims. Such permutationsare expressly within the scope of this disclosure.

What is claimed is:
 1. A voltage-matched multijunction solar cellcomprising: CdTe pn junction layers comprising a CdTe upper sub-cell;lower pn junction layers comprising a lower sub-cell; and a transparentinsulating layer positioned between the upper sub-cell CdTe pn junctionlayers and the lower sub-cell pn junction layers; wherein the CdTe uppersub-cell further comprises a transparent superstrate positioned oppositethe CdTe pn junction layers from the transparent insulating layer; andwherein serially connected strings of the CdTe upper sub-cells andserially connected strings of the lower sub-cells, each withsubstantially equivalent output voltage, are connected in parallel toform a two-terminal voltage matched solar cell.
 2. The voltage-matchedmultijunction solar cell of claim 1 wherein the lower pn junction layerscomprising a lower sub-cell comprise Si pn junction layers.
 3. Thevoltage-matched multijunction solar cell of claim 2 further comprising:a transparent first front contact and a transparent first back contactassociated with the CdTe upper sub-cell, wherein the transparent backcontact is positioned between the transparent insulating layer and theCdTe upper sub-cell; an interdigitated p-type and n-type back contactassociated with the Si lower sub-cell on the side of the Si lowersub-cell opposite the transparent insulating layer.
 4. Thevoltage-matched multijunction solar cell of claim 1, further comprising:a transparent first front contact and a transparent first back contactassociated with the CdTe upper sub-cell, wherein the transparent backcontact is positioned between the transparent insulating layer and theCdTe upper sub-cell; and a transparent second front contact and a secondback contact associated with the lower sub-cell, wherein the transparentsecond front contact is positioned between the transparent insulatinglayer and the lower sub-cell.
 5. The voltage-matched multijunction solarcell of claim 1 wherein the lower sub-cell comprises thin crystalline pnjunction layers having a thickness of equal to or less than 80micrometers.
 6. The voltage-matched multijunction solar cell of claim 1further comprising: at least one of a single crystalline orpolycrystalline CdTe upper sub-cell; and at least one of a singlecrystalline or polycrystalline Si lower sub-cell.
 7. The voltage-matchedmultijunction solar cell of claim 1 wherein the CdTe pn junction layerscomprise a CdTe absorber layer and a cadmium sulfide (CdS) emitterlayer.
 8. The voltage-matched multijunction solar cell of claim 1further comprising: a first string of serially connected CdTe uppersub-cells defined within the CdTe pn junction layers; a second string ofserially connected lower sub-cells defined within the lower pn junctionlayers; and wherein the first string and the second string each havesubstantially equal output voltages and are connected in parallelforming a two-terminal voltage matched solar cell.
 9. Thevoltage-matched multijunction solar cell of claim 1, wherein thetransparent insulating layer comprises an oxide grown on the lowersub-cell.
 10. The voltage-matched multijunction solar cell of claim 1wherein the transparent superstate layer comprises glass.
 11. A methodof fabricating a voltage-matched multijunction solar cell comprising:providing a transparent substrate having a deposition surface; forming astring of serially connected cadmium telluride (CdTe) upper sub-cells onthe deposition surface of the superstrate comprising CdTe pn junctionlayers; independently forming a string of serially connected lowersub-cells comprising lower pn junction layers; providing a transparentinsulating layer between the CdTe pn junction layers, opposite thetransparent superstrate, and the lower pn junction layers; joining theCdTe pn junction layers and the lower pn junction layers such that theCdTe upper sub-cell is positioned in a superstrate configuration; andconnecting the CdTe upper sub-cell strings and the Si lower sub-cellstrings, each with substantially similar output voltage, in parallel toform a two-terminal voltage matched solar cell.
 12. The method of claim11, further comprising independently forming a string of seriallyconnected Si lower sub-cells comprising Si lower pn junction layers. 13.The method of claim 12, further comprising: forming a first frontcontact and a first back contact associated with the CdTe uppersub-cell, wherein the transparent back contact is positioned between thetransparent insulating layer and the CdTe upper sub-cell and accessiblefrom a surface of the CdTe upper sub-cell opposite the transparentsuperstrate; and forming an interdigitated p-type and n-type backcontact associated with the Si lower sub-cell on the side of the Silower sub-cell opposite the transparent insulating layer.
 14. The methodof claim 11, further comprising: forming a first front contact and afirst back contact associated with the CdTe upper sub-cell, wherein thetransparent back contact is positioned between the transparentinsulating layer and the CdTe upper sub-cell and accessible from asurface of the CdTe upper sub-cell opposite the transparent superstrate;and forming second front contacts and second back contacts associatedwith the lower sub-cell, which second front contacts and second backcontacts are formed on opposite sides of the lower pn junction layer.15. The method of claim 11, further comprising: physically supportingthe lower sub-cell with the superstrate CdTe upper sub-cell; wherein thelower sub-cell comprises a thin crystalline pn junction layers having athickness of equal to or less than 80 micrometers.
 16. The method ofclaim 11, wherein forming a CdTe upper sub-cell comprises forming a CdTeabsorber layer and a cadmium sulfide (CdS) emitter layer.
 17. The methodof claim 11, further comprising: forming a first string of seriallyconnected CdTe upper sub-cells defined within the CdTe pn junctionlayers deposited on the surface of the transparent superstrate; forminga second string of serially connected Si lower sub-cells defined withinthe Si pn junction layers; and connecting the first string and thesecond string to form a two-terminal voltage matched solar cell.
 18. Themethod of claim 11, wherein providing a transparent insulating layerfurther comprises forming an oxide layer on the lower pn junctionlayers.
 19. The method of claim 11, wherein providing a transparentinsulating layer further comprises bonding a first side of thestandalone insulating layer to the CdTe upper sub-cell and bonding asecond side of the standalone insulating layer opposite the first sideto the lower sub-cell.
 20. The method of claim 11, wherein joining theCdTe pn junction layers and the Si pn junction layers comprises bondingthe CdTe upper sub-cell and Si lower sub-cell to a polyethyleneterephthalate insulating layer.